PCIe 6.0 alignment; EMIB flow; next phase of the CHIPS Act; managing many large files.
Reela Samuel of Cadence examines the critical role of PCIe 6.0 equalization in maintaining signal integrity and offers solutions to mitigate verification issues, such as creating validators to verify all symbols of TS0, ensuring encryption is functioning correctly, and monitoring phase and LTSSM state transitions.
John McMillan of Siemens presents an advanced packaging workflow for Intel’s Embedded Multi-die Interconnect Bridge (EMIB) technology, including technical challenges, design methodologies, and the integration of EMIBs into system-level package designs.
Dustin Todd of Synopsys examines what happens next with the U.S. CHIPS and Science Act, including the creation of the National Semiconductor Technology Center and the allocation of $13 billion for research and development efforts.
Keysight’s Roberto Piacentini Filho examines the challenges of managing large design files and massive amounts of data involved in a modern chip design project, which can consume up to a terabyte of disk space and contain hundreds of thousands of files.
Sandeep Mistry of Arm shows how ML models developed for mobile computer vision applications, which require tens to hundreds of millions of multiply and accumulate operations (MACs) per inference, can be deployed on a modern microcontroller.
Aliyah Mallak of Ansys is exploring an approach to manufacturing biotechnology products in microgravity and how simulation can be used to ensure that payloads carrying delicate, temperature-sensitive spore samples and bioreactors make it safely to the International Space Station or low Earth orbit.
Amit Srivastava of Micron Technology, Brian Coppa of ULVAC and Mark da Silva of SEMI propose addressing corporate sustainability goals with a bottom-up approach that leverages various sensor technologies at the cleanroom, sub-factory and plant level for both greenfield and brownfield device manufacturing facilities to enable predictive analytics.
And don’t miss the blogs in the latest Manufacturing, Packaging & Materials newsletter:
JeongMin Ju of Amkor shows how to prevent critical failures in copper RDLs due to melting caused by overcurrent.
Al Blais of Synopsys discusses curve line checking and fracturing requirements for the MULTIGON era.
Dempsey Deng of Lam Research compares the parasitic capacity of a 6F2 Honeycomb DRAM device to a 4F2 VCAT DRAM structure.
Jessica Albright of Brewer Science covers delamination methods, heat, topography, adhesion and thickness variation.
SEMI’s John Cooney reviews a fireside chat between the President of SEMI Americas and the U.S. Under Secretary of State for Economic Growth, Energy and Environment on securing supply chains.
Jesse Allen
(all posts)
Jesse Allen is Knowledge Center Administrator and Senior Editor at Semiconductor Engineering.
