In early June, Samsung updated its Angstrom-era roadmap, saying that its 2nm node optimized with Backside Power Delivery Network (BSPDN), or SF2Z, will enter mass production in 2027. According to the latest report from Korea Economic Daily, BSPDN is expected to reduce the size of Samsung’s 2nm chip by 17% compared to traditional front-end power delivery technology.
Citing Lee Sungjae, vice president of the Foundry PDK Development Team at Samsung, Thursday’s report also said that by applying BSPDN to its 2nm chips, Samsung is expected to improve the product’s performance and power efficiency by 8% and 15%, respectively.
Lee’s comments were the first time a Samsung foundry executive had publicly disclosed details of its BSPDN roadmap. The report explains that putting the power rails on the back of the wafer to eliminate bottlenecks between power and signal lines would make it easier to produce smaller chips.
However, Samsung is not the first semiconductor giant to use this technology. Among the Big Three in the foundry sector, Intel is leading the way and aims to produce chips with BSPDN technology, which it calls PowerVia, on Intel 20A (2 nm) in 2024. The tech giant also plans to implement PowerVia on Intel’s 20A along with the RibbonFET architecture for the full-surround gate transistor.
According to Intel, power lines typically take up about 20% of the chip surface area, while the proprietary PowerVia rear power supply technology saves this space, allowing more flexibility in the interconnect layers.
On the other hand, leading chipmaker TSMC reportedly plans to integrate its backside power delivery technology, Super PowerRail architecture, and nanosheet transistors into its A16 chip in 2026.
In addition to BSPDN, Samsung also revealed its roadmap for the next-generation Gate All Around (GAA) technology, which the company will first unveil in 2022, according to the report.
Samsung plans to start mass production of 3nm chips based on its second-generation GAA (SF3) technology in the second half of 2024 and will also implement GAA in its upcoming 2nm process, the report said.
According to Lee, SF3 has increased chip performance by 30%, improved power efficiency by 50% and reduced chip size by 35% compared to chips made using the first-generation GAA process. Combined with the introduction of BSPDN, the two technologies can further reduce chip size for Samsung.
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(Image credit: Samsung)
Please note that this article quotes information from the Korea Economic Daily.
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